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| Preliminary GS88218/36B-11/11.5/100/80/66 119-Bump BGA Commercial Temp Industrial Temp 1.14 9/2000Features * FT pin for user-configurable flow through or pipeline operation * Single/Dual Cycle Deselect Selectable * IEEE 1149.1 JTAG Compatible Boundary Scan * On-chip write parity checking; even or odd selectable * ZQ mode pin for user-selectable high/low output drive strength * x16/x32 mode with on-chip parity encoding and error detection * 3.3 V +10%/-5% core power supply * 2.5 V or 3.3 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Default to SCD x18/x36 Interleaved Pipelined mode * Byte Write (BW) and/or Global Write (GW) operation * Common data inputs and data outputs * Clock Control, registered, address, data, and control * Internal self-timed write cycle * Automatic power-down for portable applications * 119-bump BGA package -11 -11.5 -100 -80 -66 10 ns 10 ns 12.5 ns 15 ns Pipeline tCycle 10 ns 4.0 ns 4.0 ns 4.0 ns 4.5 ns 5 ns 3-1-1-1 tKQ IDD 225 mA 225 mA 225 mA 200 mA 185 mA 512K x 18, 256K x 36 ByteSafeTM 100 MHz-66 MHz 3.3 V VDD 8Mb S/DCD Sync Burst SRAMs 3.3 V and 2.5 V I/O on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output Register can be controlled by the user via the FT mode bump (Bump 5R). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. SCD and DCD Pipelined Reads The GS88218/36B is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input on Bump 4L. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Flow Through 2-1-1-1 11 ns 11.5 ns 12 ns 14 ns 18 ns tKQ 15 ns 15 ns 15 ns 15 ns 20 ns tCycle 180 mA 180 mA 180 mA 175 mA 165 mA IDD Functional Description Applications The GS88218/36B is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. ByteSafeTM Parity Functions The GS88218/36B features ByteSafe data security functions. See "ByteSafeTM Parity Functions" on page 8 for further information. FLXDriveTM The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart on page 38 for details. Controls Addresses, data I/Os, chip enables (E1 and E2), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded Rev: 1.14 9/2000 1/37 Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS88218/36B operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit. (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 GS88236 Pad Out 119-Bump BGA--Top View 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC4 DQC3 VDDQ DQC2 DQC1 VDDQ DQD1 DQD2 VDDQ DQD3 DQD4 NC NC VDDQQ 2 A6 E2 A5 DQC9 DQC8 DQC7 DQC6 DQC5 VDD DQD5 DQD6 DQD78 DQD8 DQD9 A2 NC TMS 3 A7 A4 A3 VSS VSS VSS BC VSS DP VSS BD VSS VSS VSS LBO A10 TDI 4 ADSP ADSC VDD ZQ E1 G ADV GW VDD CK SCD BW A1 A0 VDD A11 TCK 5 A8 A15 A14 VSS VSS VSS BB VSS QE VSS BA VSS VSS VSS FT A12 TDO 6 A9 A17 A16 DQB9 DQB8 DQB7 DQB6 DQB5 VDD DQA5 DQA6 DQA7 DQA8 DQA9 A13 NC NC 7 VDDQ NC NC DQB4 DQB3 VDDQ DQB2 DQB1 VDDQ DQA1 DQA2 VDDQ DQA3 DQA4 PE ZZ VDDQ Rev: 1.14 9/2000 2/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 GS88218 Pad Out 119-Bump BGA--Top View 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB1 NC VDDQ NC DQB4 VDDQ NC DQB6 VDDQ DQB8 NC NC NC VDDQ 2 A6 E2 A5 NC DQB2 NC DQB3 NC VDD DQB5 NC DQB7 NC DQB9 A2 A10 TMS 3 A7 A4 A3 VSS VSS VSS BB VSS DP VSS NC VSS VSS VSS LBO A11 TDI 4 ADSP ADSC VDD ZQ E1 G ADV GW VDD CK SCD BW A1 A0 VDD NC TCK 5 A8 A15 A14 VSS VSS VSS NC VSS QE VSS BA VSS VSS VSS FT A12 TDO 6 A9 A17 A16 DQA9 NC DQA7 NC DQA5 VDD NC DQA3 NC DQA2 NC A13 A18 NC 7 VDDQ NC NC NC DQA8 VDDQ DQA6 NC VDDQ DQA4 NC VDDQ NC DQA1 PE ZZ VDDQ Rev: 1.14 9/2000 3/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 GS88218/36 BGA Pin Description Pin Location P4, N4 A2, A3, A5, A6, B3, B5, B6, C2, C3, C5, C6, R2, R6, T3, T5 T4 T2, T6 T2, T6 K7, K6, L7, L6, M6, N7, N6, P7, P6 H7, H6, G7, G6, F6, E7, E6, D7, D6 H1, H2, G1, G2, F2, E1, E2, D1, D2 K1, K2, L1, L2, M2, N1, N2, P1, P2 L5, G5, G3, L3 P7, N6, L6, K7, H6, G7, F6, E7, D6 D1, E2, G2, H1, K2, L1, M2, N1, P2 L5, G3 P6, N7, M6, L7, K6, H7, G6, E6, D7, D2, E1, F2, G1, H2, K1, L2, N2, P1, G5, L3, T4 K4 M4 H4 E4 B2 F4 G4 A4, B4 T7 R5 R3 L4 R7 J3 J5 D4 B1, C1, R1, T1, B7, C7, U6 Symbol A0, A1 An An NC An DQA1-DQA9 DQB1-DQB9 DQC1-DQC9 DQD1-DQD9 BA, BB, BC, BD DQA1-DQA9 DQB1-DQB9 BA, BB NC CK BW GW E1 E2 G ADV ADSP, ADSC ZZ FT LBO SCD PE DP QE ZQ NC Typ e I I I -- I I/O I I/O I -- I I I I I I I I I I I I I I O I -- Description Address field LSBs and Address Counter Preset Inputs Address Inputs Address Inputs (x36 Version) No Connect (x36 Version) Address Inputs (x18 Version) Data Input and Output pins (x36 Version) Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version) Data Input and Output pins (x18 Version) Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version) No Connect (x18 Version) Clock Input Signal; active high Byte Write--Writes all enabled bytes; active low Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Single Cycle Deselect/Dual Cycle Deselect Mode Control Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) Data Parity Mode Input; 1 = Even, 0 = Odd Parity Error Out; Open Drain Output FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) No Connect Rev: 1.14 9/2000 4/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 GS88218/36 BGA Pin Description Pin Location U2 U3 U5 U4 J2, C4, J4, R4, J6 D3, E3, F3, H3, K3, M3, N3, P3, D5, E5, F5, H5, K5, M5, N5, P5 A1, F1, J1, M1, U1, A7, F7, J7, M7, U7 Symbol TMS TDI TDO TCK VDD VSS VDDQ Typ e I I O I I I I Description Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply BPR2000.002.14 Rev: 1.14 9/2000 5/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 GS88218/36 (PE = 0) Block Diagram Register A0-An D Q A0 D0 A1 D1 Q1 Counter Load A Q0 A0 A1 LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q 36 D 36 Register D BB Q 4 4 Register D BC Q Register D Q Register Register 4 D BD Q Register 36 36 36 D Q E1 E2 Register D Q 32 Parity Encode 4 Parity Compare 36 36 Register D Q FT G Power Down Control SCD ZZ DQx0-DQx9 QE D DP Note: Only x36 version shown for simplicity. Rev: 1.14 9/2000 6/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q Q D Register Preliminary GS88218/36B-11/11.5/100/80/66 GS88218/36 (PE = 1) X16x32 Mode Block Diagram Register A0-An D Q A0 D0 A1 D1 Q1 Counter Load A Q0 A0 A1 LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q 36 D 36 4 Parity Encode 32 Register D BB Q 4 Register D BC Q Q Register D Register Q Register D D BD Q Register 32 36 Register 36 D Q E1 E2 Register D Q 4 32 Parity Encode 4 Parity Compare D Q 32 Register Register D Q D Q FT G Power Down Control 32 SCD ZZ DQx0-DQx8 QE DP Note: Only x36 version shown for simplicity. Rev: 1.14 9/2000 7/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 ByteSafeTM Parity Functions In x32/x16 mode this RAM features a parity encoding and checking function. It is assumed that the RAM is being used in x32/x16 mode because there is no source for parity bits from the system. So, in x32/x16 mode, the device generates parity and stores it along with written data. It is also assumed that there is no facility for parity checking, so the RAM checks read parity and reports an error in the cycle following parity check. In x32/x16 mode the device does not drive the 9th data output, even though the internal ByteSafe parity encoding has been activated. A ByteSafe SRAM, used in x32/x16 mode, allows parity protection of data in applications where parity encoding or checking are not otherwise available. As in any system that checks read parity, reads of un-written memory locations may well produce parity errors. Initialization of the memory should be implemented to avoid this issue. In x18/x36 mode this SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are reported one clock cycle later. (See timing diagram below.) The Data Parity Mode (DP) pin must be tied high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data validity is best established at the data's destination. The Parity Error Output is an open drain output and drives low to indicate a parity error. Multiple Parity Error Output pins may share a common pull-up resistor. x32 Mode (PE = 1) Read Parity Error Output Timing Diagram CK Address A Address B Address C Address D Address E Address F Flow Through Mode DQ D Out A tKQ tLZ D Out B tHZ tKQX Err A D Out C D Out D D Out E QE Err C Pipelined Mode DQ D Out A tKQ tLZ D Out B tHZ tKQX Err A D Out C D Out D QE Err C Rev: 1.14 9/2000 8/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 x18/x36 Mode (PE = 0) Write Parity Error Output Timing Diagram CK DQ Flow Through Mode D In A tKQ tLZ D In B tHZ tKQX Err A D In C D In D D In E QE Err C Pipelined Mode DQ D In A D In B tKQ tLZ D In C tHZ tKQX Err A D In D D In E QE Err C BPR 1999.05.18 Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Single / Dual Cycle Deselect Control ByteSafe Data Parity Control Parity Enable FLXDrive Output Impedance Control Rev: 1.14 9/2000 Pin Name LBO FT ZZ SCD DP PE ZQ 9/37 State L H or NC L H or NC L or NC H L H or NC L H or NC L or NC H L H or NC Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Dual Cycle Deselect Single Cycle Deselect Check for Odd Parity Check for Even Parity Activate 9th I/Os (x18/36 Mode) Deactivate 9th I/Os (x16/32 Mode) High Drive (Low Impedance) Low Drive (High Impedance) (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Note: There are pull-up devices on the LBO, ZQ, SCD, DP and FT pins and a pull down device on the PE and ZZ pins, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table. Enable / Disable Parity I/O Pins This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits generated and read into the ByteSafe parity circuits. Burst Counter Sequences Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 1st address 2nd address 3rd address 4th address Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 BPR 1999.05.18 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. Byte Write Truth Table Function Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes Write all bytes GW H H H H H H H L BW H L L L L L L X BA X H L H H H L X BB X H H L H H L X BC X H H H L H L X BD X H H H H L L X Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes "C" and "D" are only available on the x36 version. Rev: 1.14 9/2000 10/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Synchronous Truth Table Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None External External External Next Next Next Next Current Current Current Current State Diagram Key5 X X X R R W CR CR CW CW E1 H L L L L L X H X H X H X H E22 (x36only) ADSP ADSC X L H L H H H X H X H X H X L X L X L L H H H H H H H H ADV X X X X X X L L L L H H H H W3 X X X X F T F F T T F F T T DQ4 High-Z High-Z High-Z Q Q D Q Q D D Q Q D D X F F T T T X X X X X X X X Notes: 1. X = Don't Care, H = High, L = Low 2. For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as "Q" in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.14 9/2000 11/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Simplified State Diagram X Deselect W W Simple Synchronous Operation R R X CW First Write R CR First Read X CR Simple Burst Synchronous Operation W R X Burst Write CR CW R Burst Read X CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1and E2) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.14 9/2000 12/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Simplified State Diagram with G X Deselect W W X W CW R R First Write R CR First Read X CR CW W X Burst Write R CR W CW R X Burst Read CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G. 2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.14 9/2000 13/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value -0.5 to 4.6 -0.5 to VDD -0.5 to 6 -0.5 to VDDQ +0.5 ( 4.6 V max.) -0.5 to VDD +0.5 ( 4.6 V max.) +/-20 +/-20 1.5 -55 to 125 -55 to 125 Unit V V V V V mA mA W oC oC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Parameter Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol VDD VDDQ VIH VIL TA TA Min. 3.135 2.375 1.7 -0.3 0 -40 Typ. 3.3 2.5 -- -- 25 25 Max. 3.6 VDD VDD +0.3 0.8 70 85 Unit V V V V C C Notes 1 2 2 3 3 Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V VDDQ 2.375 V (i.e., 2.5 V I/O) and 3.6 V VDDQ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be -2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC. Rev: 1.14 9/2000 14/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Undershoot Measurement and Timing VIH VDD + 2.0 V VSS 50% VSS - 2.0 V 20% tKC VIL 50% VDD Overshoot Measurement and Timing 20% tKC Capacitance (TA = 25oC, f = 1 MHZ, VDD = 3.3 V) Parameter Input Capacitance Input/Output Capacitance Note: These parameters are sample tested. Symbol CIN CI/O Test conditions VIN = 0 V VOUT = 0 V Typ. 4 6 Max. 5 7 Unit pF pF Package Thermal Characteristics Rating Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP) Layer Board single four -- Symbol RJA RJA RJC Max 40 24 9 Unit C/W C/W C/W Notes 1,2 1,2 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1.14 9/2000 15/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Conditions 2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50 VT = 1.25 V * Distributed Test Jig Capacitance Output Load 2 2.5 V 30pF* DQ 5pF* 225 225 DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current Mode Pin Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IINZZ IINM IOL VOH VOH VOL Test Conditions VIN = 0 to VDD VDD VIN VIH 0 V VIN VIH VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDD IOH = -8 mA, VDDQ = 2.375 V IOH = -8 mA, VDDQ = 3.135 V IOL = 8 mA Min -1 uA -1 uA -1 uA -300 uA -1 uA -1 uA 1.7 V 2.4 V -- Max 1 uA 1 uA 300 uA 1 uA 1 uA 1 uA -- -- 0.4 V Rev: 1.14 9/2000 16/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Operating Currents -11 Parameter Test Conditions Device Selected; All other inputs VIH or VIL Output open Symbol IDD Pipeline IDD Flow-Thru ISB Pipeline ISB Flow-Thru IDD Pipeline IDD Flow-Thru 0 to 70C 225 180 30 30 80 65 -40 to 85C 235 190 40 40 90 75 -11.5 0 to 70C 225 180 30 30 80 65 -40 to 85C 235 190 40 40 90 75 -100 0 to 70C 225 180 30 30 80 65 -40 to 85C 235 190 40 40 90 75 0 to 70C 200 175 30 30 70 55 -80 -40 to 85C 210 185 40 40 80 65 0 to 70C 185 165 30 30 60 50 -66 -40 to 85C 195 175 40 40 70 60 Unit Operating Current mA mA mA mA mA mA Standby Current ZZ VDD - 0.2V Deselect Current Device Deselected; All other inputs VIH or VIL Rev: 1.14 9/2000 17/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 AC Electrical Characteristics Parameter Clock Cycle Time Pipeline Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time FlowThru Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ 1 -11 Min 10 -- 1.5 1.5 15.0 -- 3.0 3.0 1.7 2 1.5 -- 0 -- 1.5 0.5 5 1 20 Max -- 4.0 -- -- -- 11.0 -- -- -- -- 4.0 4.0 -- 4.0 -- -- -- -- -- 10 -- -11.5 Min Max -- 4.0 -- -- -- 11.5 -- -- -- -- 4.2 4.2 -- 4.2 -- -- -- -- -- 10 -- 1.5 1.5 -100 Min Max -- 4.0 -- -- -- 12.0 -- -- -- -- 4.5 4.5 -- 4.5 -- -- -- -- -- Min 12.5 -- 1.5 1.5 15.0 -- 3.0 3.0 2 2.2 1.5 -- 0 -- 2.0 0.5 5 1 20 -80 Max -- 4.5 -- -- -- 14.0 -- -- -- -- 4.5 4.5 -- 4.5 -- -- -- -- -- Min 15 -- 1.5 1.5 20.0 -- 3.0 3.0 2.3 2.5 1.5 -- 0 -- 2.0 0.5 5 1 20 -66 Max -- 5.0 -- -- -- 18.0 -- -- -- -- 4.8 4.8 -- 4.8 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5 1.5 15.0 -- 3.0 3.0 1.7 2 1.5 -- 0 -- 2.0 0.5 5 1 20 tKC tKQ tKQX tLZ1 tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tS tH tZZS2 tZZH2 tZZR 15.0 -- 3.0 3.0 2 2.2 1.5 -- 0 -- 2.0 0.5 5 1 20 Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.14 9/2000 18/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Write Cycle Timing Single Write Burst Write Write Deselected CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH ADV must be inactive for ADSP Write WR2 WR3 A0-An WR1 tS tH GW tS tH BW tS tH BA-BD tS tH WR1 WR1 WR2 WR3 WR3 E1 masks ADSP E1 tS tH Deselected with E2 E2 E2 only sampled with ADSP or ADSC G tS tH Write specified byte for 2A and all bytes for 2B, 2C& 2D D2A D2B D2C D2D D3A DQA-DQD Hi-Z D1A Rev: 1.14 9/2000 19/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Flow Through Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0-An RD1 tS RD2 RD3 tH GW tS tH BW BA-BD tS tH E1 masks ADSP E1 tS tH E2 only sampled with ADSP or ADSC Deselected with E2 E2 tOE tOHZ G tOLZ tKQX Q1A tLZ tHZ tKQ Q2A Q2B Q2c Q2D Q3A tKQX DQA-DQD Hi-Z Rev: 1.14 9/2000 20/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Flow Through Read-Write Cycle Timing Single Read Single Write Burst Read CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0-An RD1 WR1 RD2 tS tH GW tS tH BW tS tH BA-BD tS tH WR1 E1 masks ADSP E1 tS tH E2 only sampled with ADSP and ADSC E2 tOE tOHZ G tKQ tS Q1A tH Q2A Q2B Q2c Q2D Q2A DQA-DQD Hi-Z D1A Burst wrap around to it's initial state Rev: 1.14 9/2000 21/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Pipelined SCD Read - Write Cycle Timing Single Read tKL Single Write Burst Read CK tS tH tKH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0-An RD1 WR1 RD2 tS tH GW tS tH BW tS tH BWA-BWD tS tH WR1 E1 masks ADSP E1 tS tH E2 only sampled with ADSP and ADSC E2 tOE tOHZ G tKQ tS tH Q1A D1A Q2A Q2B Q2c Q2D DQA-DQD Hi-Z Rev: 1.14 9/2000 22/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Pipelined SCD Read Cycle Timing Single Read Burst Read tKH tKL tKC ADSP is blocked by E inactive CK tS tH ADSP ADSC tS tH tS tH ADSC initiated read Suspend Burst ADV tS tH A0-An RD1 tS RD2 RD3 tH GW tS tH BW BWA-BWD tS tH E1 masks ADSP E1 tS tH E2 only sampled with ADSP or ADSC Deselected with E2 E2 tOE G DQA-DQD Hi-Z tOLZ Q1A tLZ tOHZ tKQX Q2A Q2B Q2c Q2D tKQX Q3A tHZ tKQ Rev: 1.14 9/2000 23/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Pipelined DCD Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tS tH ADSC initiated read tKC ADSP is blocked by E1 inactive ADSP ADSC tS tH Suspend Burst ADV tS tH A0-An GW RD1 tS RD2 RD3 tH tS tH BW BA-BD tS tH E1 masks ADSP E1 tS tH E2 only sampled with ADSP or ADSC E2 tOE G tOHZ Hi-Z tOLZ Q1A tLZ tHZ tKQ tKQX Q2A Q2B Q2c Q2D tKQX Q3A DQA-DQD Rev: 1.14 9/2000 24/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Pipelined DCD Read-Write Cycle Timing Single Write Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC ADV tS tH tS tH A0-An RD1 WR1 RD2 tS tH GW tS tH tH tS BW BA-BD tS tH WR1 E1 masks ADSP E1 tS tH E2 only sampled with ADSP and ADSC E2 tOE tOHZ G DQA-DQD Hi-Z tKQ Q1A tS tH D1a Q2A Q2B Q2c Q2D Rev: 1.14 9/2000 25/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Sleep Mode Timing Diagram CK tS tH tKC tKH tKL ADSP ADSC tZZS ~~~~~ ~ ~ ~~ ~ tZZH tZZR ZZ Snooze Application Tips Single and Dual Cycle Deselect SCD devices force the use of "dummy read cycles" (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP (Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. Rev: 1.14 9/2000 26/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 JTAG Pin Descriptions Pin TCK TMS Pin Name Test Clock Test Mode Select I/O In In Description Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. Output that is active depending on the state of the TAP state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDI Test Data In In TDO Test Data Out Out Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on the next falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP instructions can be used to activate the Boundary Scan Register. Rev: 1.14 9/2000 27/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 JTAG TAP Block Diagram 0 Bypass Register 210 Instruction Register TDI ID Code Register 31 30 29 TDO * * ** 210 Boundary Scan Register n ****** *** 210 TMS TCK Test Access Port (TAP) Controller Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Contents Die Revision Code GSI Technology JEDEC Vendor ID Code 1 10 9 8 7 6 5 4 3 2 1 1 0 0 0 0 0 011011001 0 011011001 0 011011001 0 011011001 Presence Register 0 1 1 1 1 Not Used I/O Configuration Bit # x36 x32 x18 x16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 1 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This device will not perform EXTEST, INTEST or the SAMPLE/PRELOAD command. Rev: 1.14 9/2000 28/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 Test Logic Reset 0 1 1 1 0 Run Test Idle Select DR 0 1 Select IR 0 1 Capture DR 0 Capture IR 0 Shift DR 1 1 0 1 Shift IR 1 0 Exit1 DR 0 Exit1 IR 0 Pause DR 1 0 Pause IR 1 0 Exit2 DR 1 0 Exit2 IR 1 0 Update DR 1 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the Rev: 1.14 9/2000 29/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the UpdateDR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This functionality is not Standard 1149.1-compliant. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not 1149.1-compliant. Nevertheless, this RAM's TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction register the RAM responds just as it does in response to the BYPASS instruction described above. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. JTAG TAP Instruction Set Summary Instruction EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD GSI RFU BYPASS Code 000 001 010 011 100 101 110 111 Description Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. This RAM does not implement 1149.1 EXTEST function. *Not 1149.1 Compliant * Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant * GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Places Bypass Register between TDI and TDO. Notes 1 1, 2 1 1 1 1 1 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.14 9/2000 30/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Test Port Input High Voltage Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Symbol Min. VIHT VILT IINTH IINTL IOLT VOHT VOLT 1.7 -0.3 -300 -1 -1 2.4 -- Max. VDD +0.3 0.8 1 1 1 -- 0.4 Unit Notes V V uA uA uA V V 1, 2 1, 2 3 4 5 6, 7 6, 8 Notes: 1. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 2. Input Under/overshoot voltage must be -2 V > Vi < V DD +2 V with a pulse width not to exceed 20% tTKC. 3. VDD VIN VIL 4. 0 V VIN VIL 5. Output Disable, VOUT = 0 to VDD 6. The TDO output driver is served by the VDD supply. 7. IOH = -4 mA 8. IOL = +4 mA JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Notes: 1. Include scope and jig capacitance. Conditions 2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V DQ JTAG Port AC Test Load 50 VT = 1.25 V * Distributed Test Jig Capacitance 30pF* Rev: 1.14 9/2000 31/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 JTAG Port Timing Diagram tTKH TCK tTKL tTKC tTS TMS TDI TDO tTKQ tTH JTAG Port AC Electrical Characteristics Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 20 -- 10 10 5 5 Max -- 10 -- -- -- -- Unit ns ns ns ns ns ns Rev: 1.14 9/2000 32/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 GS88218/36B BGA Boundary Scan Register Order Order x36 PE PH = 0 A10 A11 A12 A13 A14 A15 A16 x36 = DQA9 x32 = NA = 0 x18 x36 x18 x36 A9 A8 ADV ADSP ADSC G BW GW CK PH = 0 PH = 0 A17 BA BB BC BD CE2 CE1 A7 A6 x36 =DQC9 x32 = NA = 0 x18 Order Bump 7R n/a 3T 2T 4T 3T 5T 6R 5C 5B 6C Bump x36 x18 x36 DP SCD DQD1 DQD2 DQD5 DQD6 DQD3 DQD4 DQD7 DQD8 x36 = DQD9 x32 = NA = 0 x18 Bump x36 x18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 DQB5 DQB1 DQB2 DQB6 DQB3 DQB4 DQB7 DQB8 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6T 6A 5A 4G 4A 4B 4F 4M 4H 4K n/a n/a 6B 5L BB NC = 1 NC = 1 5G 3G 3G 5G 3L 2B 4E 3A 2A NC = 1 NC = 1 NC = 1 NC = 1 NC = 1 DQB1 DQB2 DQB3 DQB4 2D 1E 2F 1G 2H 1D 2E 2G 1H 5R 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 3J 4L DQB5 DQB6 DQB7 DQB8 2K 1L 2M 1N 2P x18 = DQB9 1K x16 = NA = 0 NC = 1 NC = 1 NC = 1 NC = 1 2L 2N 1P 2P 1K 3R 2C 3B 3C 2R 4N 4P 4D NC = 1 NC = 1 NC = 1 NC = 1 NC = 1 DQA1 DQA2 DQA3 DQA4 6P 7N 6M 7L 6K 7P 6N 6L 7K 7T 5J DQA8 DQA4 DQA3 DQA7 DQA6 DQA5 DQA2 DQA1 ZZ QE LBO A5 A4 A3 A2 A1 A0 ZQ DQA5 DQA6 DQA7 DQA8 6H 7G 6F 7E 6D BPR 1999.08.11 DQC8 DQC4 DQC3 DQC7 DQC6 DQC5 DQC2 DQC1 FT x18 =DQA9 7H x16 = NA = 0 NC = 1 NC = 1 NC = 1 A18 6G 6E 7D 6D x36 = DQB9 x32 = NA = 0 59 Note: 1. The Boundary Scan Register contains a number of registers that are not connected to any pin. They default to the value shown at reset. 2. Registers are listed in exit order (i.e., Location 1 is the first out of the TDO pin). 3. NC = No Connect, NA = Not Active Rev: 1.14 9/2000 33/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 FLXDrive Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 0.0 -20.0 -40.0 VDD I Out I Out (mA) VOut VSS -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Down) VDDQ - V Out (Pull Up) 3.1V PD HD 3.6V PD LD 3.6V PU LD 3.1V PU HD 3.6V PD HD 3.1V PU LD 3.3V PD HD 3.3V PU LD 3.3V PD LD 3.3V PU HD 3.1V PD LD 3.6V PU HD BPR 2000.02.14 Rev: 1.14 9/2000 34/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Package Dimensions--119 Pin BGA Pin 1 Corner A 7654321 G P B S D A B C D E F G H J K L M N P R T U N Top View R Bottom View Package Dimensions--119-Pin BGA T Symbol A B C D E F G Description Width Length Package Height (including ball) Ball Size Ball Height Package Height (excluding balls) Width between Balls Package Height above board Cut-out Package Width Foot Length Width of package between balls Length of package between balls Variance of Ball Height Min Nom Max 13.8 21.8 -- 0.60 0.50 -- -- 0.80 -- -- -- -- -- 14.0 22.0 -- 0.75 0.60 1.46 1.27 0.90 12.00 19.50 7.62 20.32 0.15 14.2 22.2 2.40 0.90 0.70 1.70 -- 1.00 -- -- -- -- -- K K N E P R F C S T Unit: mm Side View BPR 1999.05.18 Rev: 1.14 9/2000 35/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Ordering Information for GSI Synchronous Burst RAMs Org 514K x 18 514K x 18 514K x 18 514K x 18 514K x 18 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 514K x 18 514K x 18 514K x 18 514K x 18 514K x 18 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 Part Number1 GS88218B-11 GS88218B-11.5 GS88218B-100 GS88218B-80 GS88218B-66 GS88236B-11 GS88236B-11.5 GS88236B-100 GS88236B-80 GS88236B-66 GS88218B-11I GS88218B-11.5I GS88218B-100I GS88218B-80I GS88218B-66I GS88236B-11I GS88236B-11.5I GS88236B-100I GS88236B-80I GS88236B-66I Type ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through Package BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA Speed2 (MHz/ns) 100/11 100/11.5 100/12 80/14 66/18 100/11 100/11.5 100/12 80/14 66/18 100/11 100/11.5 100/12 80/14 66/18 100/11 100/11.5 100/12 80/14 66/18 TA3 C C C C C C C C C C I I I I I I I I I I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS88218BT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.14 9/2000 36/37 (c) 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88218/36B-11/11.5/100/80/66 Revision History DS/DateRev. Code: Old; New Types of Changes Format or Content Page;Revisions;Reason * Last Page/Fixed "GSGS.." in Ordering Information Note. * Fromatted Pin Outs and Pin Description to new small caps. * Formatted Block diagrams to new small caps. * Formatted Timing Diagrams to new small caps. * Changed "Flow thru" to "Flow Through" in Timing Diagrams. * Boundary Scan Register/Formatted to new small caps. * 5/Fixed pin description table to match pinouts. * Pin Description/Changed chip enables to match pins. * Pin Description/Took 4A out of NC x18 row. * Pin Description/Reversed 4P and 4N to be consistent with A0 and A1. * Pin Description?Changed 2H to 1H in x18 Data I/O's. * Boundary Scan Register/Corrected sequence of Data I/O pins. * Boundary Scan Register?Minor corrections and comments invisible. * Changed 4J to VDD in Pad out. * Changed 5J to QE. * First Release of 880 F. * Changed Bump 3C to 4L on first page to correspond SCD pin in BGA pinout. * Changed speed bin to 150 - 80 Mhz * Correction on page 8. x32 Mode (PE = 0) Changed to (PE = 1) * Correction on page 9. x18/x36 Mode (PE = 1) Changed to (PE = 0) * Corrections to AC Electrical Characteristics Table - Format/Typos GS88218/36BRev1.04h 5/ 1999; 1.05 9/1999I Content GS88218/36B1.05 9/ 1999I;1.06 11/1999J GS88218/36B1.06 11/ 1999J;1.07 11/1999K GS8821836 Rev 1.07 11/ 1999; GS8821836 Rev 1.08 3/2000 GS88218/36B1.0 3/2000; GS88218/36B1.0 3/2000O; Content content Content Content GS88218/36B1.0 3/2000O; 88218_r1_10 88218_r1_10; 88218_r1_11 88218_r1_11; 88218_r1_12 Content Content Content * Updated BSR table on page 37 (see order 39 & 60) * Updated ADSC, E1 and E2 on timing diagrams on pages 25, 26, & 29 * Updated diagrams on pages 8 & 9 * Updated BGA pin description to meet JEDEC standard * Deleted 150 MHz references * Changed 133 MHz references to 11 ns * Changed 117 MHz references to 11.5 ns * Used 100 MHz Pipeline mode numbers for 11 ns and 11.5 ns * Added 66 MHz speed bin * Updated format to comply with Technical Publications standards * Updated Capitance table--removed Input row and changed Output row to I/O 37/37 (c) 2000, Giga Semiconductor, Inc. 88218_r1_12; 88218_r1_13 Content/Format 88218_r1_13; 88218_r1_14 Content Rev: 1.14 9/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
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